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SECTION 2 HARDWARE DESCRIPTION

They tend to occur either a little early or late but the center

of the spread in these pulses is centered in the window.

Figure 2-15. VCO and Timing Generator

The signal PDLL (Phase Detector Lead/Lag) divides the window

into early and late sections. PDNF (Phase Detector Normal Frame)

is always true in double density. Its complement PDIF (Phase

Detector Illegal Frame) is used in single density only. In

single density, when the data pulses are separated by either 2

or 4 microseconds, every other 1 us frame of the phase detector

is an Illegal Frame for single density operation. RCLK (Read

Clock) is generated for both FM and MFM. Sections of ICs 3C, 3B,

and 4A provide this switching logic. PDPD (Phase Detector Pulse

Detected) indicates that during the last 1 us frame a data pulse

was detected. This signal is maintained during the entire frame.

PDPP (Phase Detector Pulse Present) is the output of a one-shot

with a period of 1 us. It is triggered by an incoming data

pulse. The falling edge of this signal occurs at the same place

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Qume DataTrak 8 Handbuch Seite 25