Qume DataTrak 8 Handbuch PDF herunterladen (Seite 14)

SECTION 2 HARDWARE DESCRIPTION

2.4 BUS CONTROL SIGNALS

All Control Signals from the

S100 bus are buffered by ICs 1H

and 3K before internal use. These

line receivers have schmitt

trigger inputs typically offering

400 millivolts hysteresis. See

Figure 2-3.

In some older mainframes

SLVCLR* is not implemented. For

use in those systems POC* (pin 99)

can be connected to SLVCLR* by 8

jumper (BRST* to POC*).

Figure 2-3.

Control Signal Buffers

2.5 DISK PROCESSOR CONTROL PORT

The Disk Processor Control Port is an S-100 output port which

provides the host system with control of the on-board processor.

The port is strobed by the occurrence of sOUT, pWR*, and a

matching port address (BPA*). The following functions are

implemented.

1. Switch internal memory to and from the bus.

2. Issue an interrupt to the Z80A processor

3. Reset the Z80A processor.

The board reset signal BR* brings the port to the initial

state where internal memory is switched into. the S-100 bus.

Refer to Figure 2-4 for circuit details.

SLVRQ is set by date bit O.

Asserting SLVRQ* initiates the

memory switch process. SLVRQ* is

applied to the Z80A BUSRQ* pin.

When SLVRQ* (BUSRQ*) is asserted,

the Z80A tri-states its data,

address, and control lines. The

Z80A then asserts SLVACK*

(BUSACK*). Refer to the Z80A

TECHNICAL MANUAL. Assertion of

SLVACK* enables the Memory

Control circuit to respond to 8-

100 memory cycles.

Figure 2-4. Control Port

ZINT is set by data bit 1. ZINT(*) serves a dual function.

ZINT* is the maskable interrupt request to the on-board Z80A.

Note, circuit implementation makes it possible for the on-board

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 46 47

Double D 1
. ERRATIC DISK OPERATION 4

Kommentare zu diesen Handbüchern

Keine Kommentare

Qume DataTrak 8 Handbuch Seite 14

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Drucken & Scannen Qume DataTrak 8