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APPENDIX C INTERNAL SIGNAL DEFINITIONS

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APPENDIX C

INTERNAL SIGNAL DEFINITIONS

BCPS BOARD - CONTROL PORT STROBE

BDBIN BUS - DATA BUS IN

BDI* BOARD - DATA IN

BLSTB BOARD - FUNCTION STROBE

BMA* BOARD - MEMORY ADDRESSFD

BMA BOARD - POR_ ADDRESSED

BMEMR BUS - MEMORY READ

BR* BOARD - RESET

BPWR BUS - PROCESSOR WRITE

BSINP BUS - STATUS INPUT

BSOUT BUS STATUS OUTPUT

BSWO BUS STATUS WRITE OUT

CHNG* DISK CHANGED

DCLK 1791-01 CLOCK

DCRE* 1791-01 READ ENABLE

DCWE* 1791-01 WRITE ENABLE

DDEN DOUBLE DENSITY ENABLE

DDIN* 1791-01 DISK DATA IN

DDRQ 1791-01 DATA REQUEST

DINT 1791-01 INTERRUPT REQ

DSA DRIVE SELECT A

DSB DRIVE SELECT B

DSE DRIVE SELECT ENABLE

IAnn INTERNAL ADDRESS BIT nn

IIORQ* INTERNAL Z80A I/O REQ

ILP* ILLEGAL PACK

IMREQ* INTERNAL Z80A MEM REQ

IRD* INTERNAL Z80A READ. CYCLE

IWR* INTERNAL Z80A WRITE CYCLE

MDI* MEMORY DATA IN

HDO* MEMORY DATA OUT

MSH* MEMORY PELECT HIGH

MSL* MEMORY SELECT LOW

PCA PRECOMP SELECT A

PCB PRECOMP SELECT B

PDIP PHASE DETECT ILLEGAL FRAME

PDLL PHASE DETECT LEAD/LAG

PDNF PHASE DETECT NORMAL FRAME

PDPD PHASE DETECT PULSE DETECTED

PDPP PHASE DETECT PULSE PRESENT

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Double D 1
. ERRATIC DISK OPERATION 4

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